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| IA6805E2 Microprocessor Unit FEATURES * * * * * * * * * * * Data Sheet As of Production Version 00 Form, Fit, and Function Compatible with the Harris (c) CDP6805E2CE and Motorola (c) MC146805E2 Internal 8-bit Timer with 7-Bit Programmable Prescaler On-chip Clock Memory Mapped I/O Versatile Interrupt Handling True Bit Manipulation Bit Test and Branch Instruction Vectored Interrupts Power-saving STOP and WAIT Modes Fully Static Operation 112 Bytes of RAM The IA6805E2 is a "plug-and-play" drop-in replacement for the original IC. innovASIC produces replacement ICs using its MILESTM , or Managed IC Lifetime Extension System, cloning technology. This technology produces replacement ICs far more complex than "emulation" while ensuring they are compatible with the original IC. MILESTM captures the design of a clone so it can be produced even as silicon technology advances. MILESTM also verifies the clone against the original IC so that even the "undocumented features" are duplicated. This data sheet documents all necessary engineering information about the IA6805E2 including functional and I/O descriptions, electrical characteristics, and applicable timing. Package Pinout RESET_N RW_N OSC1 VDD IRQ_N LI DS RW_N AS PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 A12 A11 A10 A9 A8 VSS 40 Pin DIP (3) (4) (5) (6) (7) (8) (9) (10) (11) (12) (13) (14) (15) (16) (17) (18) (19) (20) (38) (37) (36) (35) (34) (33) (32) (31) (30) (29) (28) (27) (26) (25) (24) (23) (22) (21) OSC2 (6) (5) (4) (3) (2) (1) (44) (43) (42) (41) (40) TIMER PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 B0 B1 B2 B3 B4 B5 A12 A11 A10 A9 A8 B7 B6 B5 VSS B4 B6 B7 NC AS PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 NC NC (7) (8) (9) (10) (11) (12) (13) (14) (15) (16) (17) (18) (19) (20) (21) (22) (23) (24) (25) (26) (27) (28) LI (2) (39) OSC1 PB0 (39) (38) NC DS IA6805E2 OSC2 RESET_N (1) (40) VDD TIMER IRQ_N PB1 PB2 PB3 PB4 PB5 PB6 PB7 B0 B1 B2 B3 IA6805E2 44 Pin LCC (37) (36) (35) (34) (33) (32) (31) (30) (29) Copyright (c) 2002 ENG21108140100 innovASIC The End of ObsolescenceTM www.innovasic.com Customer Support: 1-888-824-4184 Page 1 of 31 IA6805E2 Microprocessor Unit Description Data Sheet As of Production Version 00 The IA6805E2 (CMOS) Microprocessor Unit (MPU) is a low cost, low power MPU. It features a CPU, on-chip RAM, parallel I/O compatibility with pins programmable as input or output. The following paragraphs will further describe this system block diagram and design in more detail. TIMER PRESCALER TIMER/ COUNTER OSC1 OSC2 RESET_N TIMER CONTROL OSCILLATOR LI IRQ_N PA0 B0 ACCUMULATOR 8 PORT A REG DATA DIR REG INDEX REGISTER 8 X CONDITION CODE REGISTER 5 CC STACK POINTER 6 SP PROGRAM COUNTER HIGH 5 PCH PROGRAM COUNTER LOW 8 PCL ALU ADDRESS DRIVE A CPU CONTROL MUX BUS DRIVE B1 B2 B3 B4 B5 B6 B7 MULTIPLEXED ADDRESS DATA BUS PA0 PA1 PA2 PORT A I/O LINES PA3 PA4 PA5 PA6 PA7 CPU PB0 PB1 PB2 PORT B I/O LINES PB3 PB4 PB5 PB6 PB7 PORT B REG DATA DIR REG A8 A9 A10 A11 A12 ADDRESS BUS AS 112x8 RAM BUS CONTROL DS RW_N ADDRESS STROBE DATA STROBE READ/WRITE Figure 1. System Block Diagram Copyright (c) 2002 ENG21108140100 innovASIC The End of ObsolescenceTM www.innovasic.com Customer Support: 1-888-824-4184 Page 2 of 31 IA6805E2 Microprocessor Unit I/O Signal Description Data Sheet As of Production Version 00 The table below describes the I/O characteristics for each signal on the IC. The signal names correspond to the signal names on the pinout diagrams provided. SIGNAL NAME I/O N/A I I DESCRIPTION Source: These t w o pins provide power to the chip. V D and V SS is ground. D V D D a n d V SS (Power and Ground) RESET_n (Reset) IRQ_n (Interrupt Request) LI (Load Instruction) provides + 5 volts (0.5) p o w e r T T L : I n p u t pin t h a t c a n b e u s e d t o r e s e t t h e M P U ' s i n t e r n a l s t a t e b y p u l l i n g t h e r e s e t _ n pin low. T T L : I n p u t pin t h a t i s l e v e l a n d e d g e s e n s i t i v e . C a n b e u s e d t o r e q u e s t a n i n t e r r u p t sequence. T T L w i t h s l e w r a t e c o n t r o l : O u t p u t pin u s e d to i n d i c a t e t h a t a n e x t o p c o d e f e t c h i s in p r o g r e s s . U s e d o n l y f o r c e r t a i n d e b u g g i n g a n d t e s t s y s t e m s . N o t c o n n e c t e d in n o r m a l o p e r a t i o n . O v e r l a p s D a t a S t r o b e ( D S ) signal. T h i s o u t p u t is c a p a b l e o f d r i v i n g o n e standard TTL load and 50pF. T T L w i t h s l e w r a t e c o n t r o l : O u t p u t p i n u s e d to t r a n s f e r d a t a t o o r f r o m a p e r i p h e r a l o r m e m o r y . D S occurs a n y t i m e the M P U d o e s a d a t a read o r write a n d during data transfer t o o r f r o m i n t e r n a l m e m o r y . D S is a v a i l a b l e a t f O S C / 5 w h e n t h e M P U is n o t in t h e W A I T or STOP mode. This output is capable of driving one standard TTL load and 130pF. T T L w i t h s l e w r a t e c o n t r o l : O u t p u t pin u s e d to i n d i c a t e t h e d i r e c t i o n o f d a t a t r a n s f e r from internal m e m o r y , I / O registers, and external peripheral d e v i c e s a n d m e m o r i e s . I n d i c a t e s t o a s e l e c t e d p e r i p h e r a l w h e t h e r t h e M P U i s to r e a d ( R W _ n h i g h ) o r w r i t e ( R W _ n l o w ) data o n t h e n e x t data strobe. This o u t p u t is c a p a b l e o f d r i v i n g o n e standard TTL load and 130pF. T T L w i t h s l e w r a t e c o n t r o l : O u t p u t s t r o b e u s e d to i n d i c a t e t h e p r e s e n c e o f a n a d d r e s s o n t h e 8 - b i t m u l t i p l e x e d b u s . T h e A S l i n e i s u s e d to d e m u l t i p l e x t h e e i g h t l e a s t s i g n i f i c a n t a d d r e s s bits f r o m t h e data b u s . A S is a v a i l a b l e a t f O S C / 5 w h e n t h e M P U is n o t in t h e W A I T o r S T O P m o d e s . This o u t p u t is c a p a b l e o f d r i v i n g o n e s t a n d a r d T T L load a n d 130pF. T T L with s l e w rate c o n t r o l : T h e s e 1 6 l i n e s c o n s t i t u t e I n p u t / O u t p u t p o r t s A a n d B . E a c h l i n e is i n d i v i d u a l l y p r o g r a m m e d to b e e i t h e r a n i n p u t o r o u t p u t u n d e r s o f t w a r e c o n t r o l o f t h e D a t a D i r e c t i o n R e g i s t e r ( D D R ) a s s h o w n b e l o w in T a b l e 1 a n d F i g u r e 2 . T h e p o r t I / O is p r o g r a m m e d b y w r i t i n g t h e c o r r e s p o n d i n g b i t i n t h e D D R to a " 1 " f o r o u t p u t a n d a " 0 " f o r i n p u t . In t h e o u t p u t m o d e t h e b i t s a r e l a t c h e d a n d a p p e a r o n t h e c o r r e s p o n d i n g o u t p u t p i n s . A l l t h e D D R ' s a r e i n i t i a l i z e d to a " 0 " o n r e s e t . T h e o u t p u t p o r t registers a r e n o t initialized o n reset. E a c h o u t p u t is c a p a b l e o f d r i v i n g o n e s t a n d a r d TTL load and 50pF. T T L with s l e w rate control: T h e s e five outputs constitute the higher order n o n m u l t i p l e x e d a d d r e s s lines. E a c h o u t p u t is capable o f d r i v i n g o n e s t a n d a r d T T L l o a d a n d 130pF. T T L with slew rate c o n t r o l : T h e s e b i - d i r e c t i o n a l l i n e s c o n s t i t u t e t h e l o w e r o r d e r a d d r e s s e s and data. T h e s e lines are multiplexed with address present a t address s t r o b e t i m e a n d data p r e s e n t a t data s t r o b e t i m e . W h e n in t h e d a t a m o d e , t h e s e l i n e s a r e b i directional, transferring data to and from m e m o r y a n d peripheral devices a s indicated by t h e R W _ n p i n . A s o u t p u t s , these lines are capable o f driving o n e standard T T L load and 130pF. T T L : Input used to control the internal timer/counter circuitry. T T L O s c i l l a t o r i n p u t / o u t p u t : These p i n s provide c o n t r o l i n p u t f o r the on-chip clock o s c i l l a t o r c i r c u i t s . E i t h e r a c r y s t a l o r e x t e r n a l c l o c k i s c o n n e c t e d to t h e s e p i n s to p r o v i d e a s y s t e m c l o c k . T h e c r y s t a l c o n n e c t i o n i s s h o w n i n F i g u r e 3 . T h e O S C 1 to b u s transitions for system designs using oscillators slower than 5MHz is shown in Figure 4 . T h e c i r c u i t s h o w n i n F i g u r e 3 is r e c o m m e n d e d w h e n u s i n g a c r y s t a l . A n e x t e r n a l C M O S o s c i l l a t o r is r e c o m m e n d e d w h e n u s i n g c r y s t a l s o u t s i d e t h e s p e c i f i e d r a n g e s . T o m i n i m i z e o u t p u t distortion a n d start-up stabilization time, the crystal a n d c o m p o n e n t s should b e mounted as close to the input pins as possible. W h e n a n e x t e r n a l c l o c k i s u s e d , i t s h o u l d b e a p p l i e d to t h e O S C 1 i n p u t w i t h t h e O S C 2 input not connected, as shown in Figure 3 . O DS (Data Strobe) O RW_n (Read/Write) O AS (Address Strobe) O PA0-PA7/PB0-PB7 (Input/Output Lines) I/O A8-A12 (High Order Address Lines) O B0-B7 (Address/Data Bus) I/O Timer OSC1, OSC2 (System Clock) I I/O Crystal External Clock Table 1 Copyright (c) 2002 ENG21108140100 www.innovasic.com Customer Support: 1-888-824-4184 innovASIC The End of ObsolescenceTM Page 3 of 31 IA6805E2 Microprocessor Unit I/O Pin Functions Data Sheet As of Production Version 00 R/W-n DDR I/O Pin Functions 0 0 The I/O pin is in input mode. Data is written into the output data latch. 0 1 Data is written into the output data latch and output to the I/O pin. 1 0 The state of the I/O pin is read. 1 1 the I/O pin is in an output mode. The output data latch is read. I/O Port Circuitry and Register Configuration: DATA DIRECTION REGISTER BIT TO AND FROM LATCHED OUTPUT DATA BIT OUTPUT I/O PIN CPU INPUT REG BIT INPUT I/O PIN 7 6 5 4 3 2 1 0 $0004 ($0005) DATA DIRECTION DDA7 DDA6 DDA5 DDA4 DDA3 DDA2 DDA1 DDA0 A(B) (DDB7) (DDB6) (DDB5) (DDB4) (DDB3) (DDB2) (DDB1) (DDB0) REGISTER PORT A(B) REGISTER $0000 ($0001) PIN PA7 (PB7) PA6 (PB6) PA5 (PB5) PA4 (PB4) PA3 (PB3) PA2 (PB2) PA1 (PB1) PA0 (PB0) Figure 2. PA0-PA7/PB0-PB7 (Input/Output Lines) Copyright (c) 2002 ENG21108140100 innovASIC The End of ObsolescenceTM www.innovasic.com Customer Support: 1-888-824-4184 Page 4 of 31 IA6805E2 Microprocessor Unit Crystal Parameters Representative Frequencies: RS max C0 C1 Q COSC1 COSC2 5.0 MHz 50 8 pF 0.02 pF 50 k 15-30 pF 15-25 pF 4.0 MHz 75 7 pF 0.012 pF 40 k 15-30 pF 15-25 pF Data Sheet As of Production Version 00 1.0 MHz 400 5 pF 0.008 pF 30 k 15-40 pF 15-30 pF Oscillator Connections: CRYSTAL CIRCUIT L C1 38 OSC2 38 OSC2 C0 RS 39 OSC1 39 OSC1 ia6805E2 10 M 38 OSC2 C OSC2 39 OSC1 C OSC1 NC CRYSTAL OSCILLATOR CONNECTIONS OSC1 OSC2 39 38 IA6805E2 tOL OSC1 PIN t tOLOL tOH Figure 3. OSC1, OSC2 (System Clock) OSC1 to Bus Transitions Timing Waveforms: OSC1 AS DS RW_n A[12:8] B[7:0] MPU READ B[7:0] MPU WRITE MUX ADDR MPU READ DATA* MUX ADDR MPU WRITE DATA *READ DATA "LATCHED" ON DS FALL Figure 4. OSC1, OSC2 (System Clock) Copyright (c) 2002 ENG21108140100 innovASIC The End of ObsolescenceTM www.innovasic.com Customer Support: 1-888-824-4184 Page 5 of 31 IA6805E2 Microprocessor Unit Functional Description Memory: Data Sheet As of Production Version 00 The MPU is capable of addressing 8192 bytes of memory and I/O registers. The locations are divided into internal memory space and external memory space as shown in Figure 5. The first 128 bytes of memory contain internal port I/O locations, timer locations, and 112 bytes of RAM. The MPU can read from or write to any of these locations. During program reads from on chip locations, the MPU accepts data only from the addressed on chip location. Any read data appearing on the input bus is ignored. The shared stack area is used during interrupts or subroutine calls. A maximum of 64 bytes of RAM is available for stack usage. The stack pointer is set to $7f at power up. The unused bytes of the stack can be used for data storage or temporary work locations, but care must be taken to prevent it from being overwritten due to stacking from an interrupt or subroutine call. 0 $0000 0 1 PORT A DATA REGISTER PORT B DATA REGISTER EXTERNAL MEMORY SPACE EXTERNAL MEMORY SPACE PORT A DATA DIRECTION REGISTER PORT B DATA DIRECTION REGISTER EXTERNAL MEMORY SPACE EXTERNAL MEMORY SPACE TIMER DATA REGISTER TIMER CONTROL REGISTER I/O PORTS TIMER RAM ACCESS VIA PAGE 0 DIRECT ADDRESS 127 128 $007F $0080 2 3 4 5 6 7 255 256 $00FF $0100 8 9 10 EXTERNAL MEMORY SPACE 15 EXTERNAL MEMORY SPACE (8064 BYTES) 16 63 64 RAM (112 BYTES) TIMER INTERRUPT FROM WAIT STATE ONLY TIMER INTERRUPT INTERRUPT VECTORS 8191 EXTERNAL INTERRUPT SWI RESET $1FF6 - $1FF7 $1FF8 - $1FF9 $1FFA - $1FFB $1FFC - $1FFD $1FFE - $1FFF 127 STACK (64 BYTES MAX) Figure 5. Memory Map Copyright (c) 2002 ENG21108140100 www.innovasic.com Customer Support: 1-888-824-4184 innovASIC The End of ObsolescenceTM Page 6 of 31 IA6805E2 Microprocessor Unit Registers: Data Sheet As of Production Version 00 The following paragraphs describe the registers contained in the MPU. Figure 6 shows the programming model and Figure 7 shows the interrupt stacking order. 7 A 7 X 12 PCH 12 0 6 1 8 7 PCL 0 ACCUMULATOR 0 INDEX REGISTER 0 PROGRAM COUNTER 0 SP STACK POINTER 0 0 0 0 0 4 H I CC N Z 0 C CONDITION CODE REGISTER CARRY/BORROW ZERO NEGATIVE INTERRUPT MASK HALF CARRY Figure 6. Programming Model NOTE: Since the stack pointer decrements during pushes, the PCL is stacked first, followed by PCH, etc. Pulling from the stack is in the reverse order. STACK 1 R E T U R N 1 1 CONDITION CODE REGISTER I N T E R R U P T ACCUMULATOR INDEX REGISTER 0 0 0 PCL PCH INCREASING MEMORY ADDRESSES DECREASING MEMORY ADDRESSES UNSTACK Figure 7. Interrupt Stacking Order Copyright (c) 2002 ENG21108140100 innovASIC The End of ObsolescenceTM www.innovasic.com Customer Support: 1-888-824-4184 Page 7 of 31 IA6805E2 Microprocessor Unit A(Accumulator): Data Sheet As of Production Version 00 The accumulator is an 8-bit register used to hold operands and results of arithmetic calculations or data manipulations. X(Index Register): The index register is an 8-bit register used during the indexed addressing mode. It contains an 8-bit value used to create an effective address. The index register may also be used as a temporary storage area when not performing addressing operations. PC(Program Counter): The program counter is a 13-bit register that holds the address of the next instruction to be performed by the MPU. SP(Stack Pointer): The stack pointer is a 13-bit register that holds the address of the next free location on the stack. During an MPU reset or the reset stack pointer (RSP) instruction, the stack pointer is set to location $007f. The seven most significant bits of the stack pointer are permanently set to 0000001. They are appended to the six least significant register bits to produce an address range down to location $0040. The stack pointer gets decremented as data is pushed onto the stack and incremented as data is removed from the stack. The stack area of RAM is used to store the return address on subroutine calls and the machine state during interrupts. The maximum number of locations for the stack pointer is 64 bytes. If the stack goes beyond this limit the stack pointer wraps around and points to its upper limit thereby losing the previously stored information. Subroutine calls use 2 bytes of RAM on the stack and interrupts use 5 bytes. CC(Condition code Register): The condition code register is a 5-bit register that indicates the results of the instruction just executed. The bit is set if it is high. A program can individually test these bits and specific actions can be taken as a result of their states. Following is an explanation of each bit. C(Carry Bit): The carry bit indicates that a carry or borrow out of the Arithmetic Logical Unit (ALU) occurred during the last arithmetic instruction. This bit is also modified during bit test, shift, rotate, and branch types of instructions. Z(Zero Bit): The zero bit indicates the result of the last arithmetic, logical, or data manipulation was zero. N(Negative Bit): The negative bit indicates the result to the last arithmetic, logical, or data manipulation was negative (bit 7 in the result is high). Copyright (c) 2002 ENG21108140100 innovASIC The End of ObsolescenceTM www.innovasic.com Customer Support: 1-888-824-4184 Page 8 of 31 IA6805E2 Microprocessor Unit I(Interrupt Mask Bit) Data Sheet As of Production Version 00 The interrupt mask bit indicates that both the external interrupt and the timer interrupt are disabled (masked). If an interrupt occurs while this bit is set, the interrupt is latched and is processed as soon as the interrupt bit is cleared. H(Half Carry Bit) The half carry bit indicates that a carry occurred between bits 3 and 4 of the ALU during an ADD or ADC operation. Resets: The MPU can be reset by initial power up or by the external reset pin (reset_n). POR(Power On Reset) Power on reset occurs on initial power up. It is strictly for power initialization conditions and should not be used to detect drops in the power supply voltage. There is a 1920 tCYC time out delay from the time the oscillator is detected. If the reset_n pin is still low at the end of the delay, the MPU will remain in the reset state until the external pin goes high. Reset_n The reset_n pin is used to reset the MPU. The reset pin must stay low for a minimum of tcyc to guarantee a reset. The reset_n pin is provided with a Schmitt Trigger to improve noise immunity capability. Interrupts: The MPU can be interrupted with the external interrupt pin (irq_n), the internal timer interrupt request, or the software interrupt instruction. When any of these interrupts occur, normal processing is suspended at the end of the current instruction execution. The processor registers are saved on the stack (stacking order shown in Figure 7) and the interrupt mask (I) is set to prevent additional interrupts. Normal processing resumes after the RTI instruction causes the register contents to be recovered from the stack. When the current instruction is completed, the processor checks all pending hardware interrupts and if unmasked (I bit clear) proceeds with interrupt processing. Otherwise, the next instruction is fetched and executed. Masked interrupts are latched for later interrupt service. External interrupts hold higher priority than timer interrupts. At the end of an instruction execution, if both an external interrupt and timer interrupt are pending, the external interrupt is serviced first. The SWI gets executed with the same priority as any other instruction if the hardware interrupts are masked (I bit set). Figure 8 shows the Reset and Interrupt processing flowchart. Copyright (c) 2002 ENG21108140100 innovASIC The End of ObsolescenceTM www.innovasic.com Customer Support: 1-888-824-4184 Page 9 of 31 IA6805E2 Microprocessor Unit Data Sheet As of Production Version 00 RESET SET I BIT ? CLEAR STACK PC, X, A, CC IRQ_N EDGE ? N Y CLEAR IRQ_N REQUEST LATCH IRQ_N I_CC <= 1 SP <= $007F DDRs <= 0 CLR IRQ_N LOGIC TIMER <= $FF PRESCALER <= $7F TCR <= $7f I <= 1 TCR6=0 AND TCR7=1? PUT 1FFE,1FFF ON ADDRESS BUS N Y TIMER LOAD PC FROM: SWI: 1FFC/1FFD IRQ_N: 1FFA/1FFB TIMER: 1FF8/1FF9 TIMER WAIT:1FF6/ 1FF7 FETCH INSTRUCTION Y RESET_N PIN = LOW IN RESET ? N RESET_N PIN = LOW IS FETCHED INSTRUCTION AN SWI? N Y PC+1=>PC SWI LOAD PC FROM 1FFE/1FFF EXECUTE ALL INSTRUCTION CYCLES Figure 8. Reset and Interrupt Processing Flowchart Copyright (c) 2002 ENG21108140100 innovASIC The End of ObsolescenceTM www.innovasic.com Customer Support: 1-888-824-4184 Page 10 of 31 IA6805E2 Microprocessor Unit External Interrupt: Data Sheet As of Production Version 00 If the external interrupt pin irq_n is "low" and the interrupt mask bit of the condition code register is cleared, the external interrupt occurs. When the interrupt is recognized, the current state of the machine is pushed onto the stack and the condition code register I-bit gets set masking further interrupts until the present one is serviced. The program counter is then loaded with the contents of the interrupt vector, which contains the location of the interrupt service routine. The contents of $1FFA and $1FFB specify the address for this service routine. A functional diagram of the external interrupt is shown in Figure 9 and a mode diagram of the external interrupt is shown in Figure 10. The timing diagram shows two different treatments of the interrupt line (irq_n) to the processor. The first shows several interrupt lines "wire ORed" to form the interrupts at the processor. If the interrupt line (irq_n) remains low after servicing an interrupt, the next interrupt is recognized. The second shows single pulses on the interrupt line spaced far enough apart to be serviced. The minimum time between pulses is a function of the length of the interrupt service. After a pulse occurs, the next pulse should not occur until an RTI has occurred. The time between pulses (tILIL) is obtained by adding 20 instruction cycles to the total number of cycles it takes to complete the service routine including the RTI instruction. VDD D INTERRUPT PIN C Q R I BIT (CCR) Q EXTERNAL INTERUPT REQUEST POWER-ON RESET EXTERNAL RESET EXTERNAL INTERRUPT BEING SERVICED Figure 9. Interrupt Functional Diagram Copyright (c) 2002 ENG21108140100 innovASIC The End of ObsolescenceTM www.innovasic.com Customer Support: 1-888-824-4184 Page 11 of 31 IA6805E2 Microprocessor Unit Data Sheet As of Production Version 00 Figure 10. Interrupt Mode Diagram Timer Interrupt: If the timer mask bit (TCR6) and the interrupt mask bit (I) of the condition code register are cleared, each time the timer decrements to zero ($01 to $00 transition) an interrupt request is generated. When the interrupt is recognized, the current state of the machine is pushed onto the stack and the condition code register I-bit gets set masking further interrupts until the present one is serviced. The program counter is then loaded with the contents of the timer interrupt vector, which contains the location of the timer interrupt service routine. The contents of $1FF8 and $1FF9 specify the address for this service routine. If the MPU is in the wait mode and a timer interrupt occurs, then the contents of $1FF6 and $1FF7 specify the service routine. When the timer interrupt service routine is complete, the software executes an RTI instruction to restore the machine state and starts executing the interrupt program. Software Interrupt: Software interrupt is an executable instruction regardless of the state of the interrupt mask bit (I) in the condition code register. SWI is similar to hardware interrupts. It executes after the other interrupts if the interrupt mask bit is zero. The contents of $1FFC and $1FFD specify the address for this service routine. Low Power Modes: The low power modes consist of the stop instruction and the wait instruction. following paragraphs explain these modes of operation. The Copyright (c) 2002 ENG21108140100 innovASIC The End of ObsolescenceTM www.innovasic.com Customer Support: 1-888-824-4184 Page 12 of 31 IA6805E2 Microprocessor Unit Stop Modes: Data Sheet As of Production Version 00 The stop instruction places the MPU in low power consumption mode. The stop instruction disables clocking of most internal registers. Timer control register bits 6 and 7 (TCR6 and TCR7) are altered to remove any pending timer interrupt requests and to disable any further timer interrupts. The DS and AS output lines go "low" and the RW_n line goes "high". The multiplexed address/data bus goes to the data input state. The high order address lines remain at the address of the next instruction. External interrupts are enabled by clearing the I bit in the condition code register. All other registers, memory, and I/O remain unaltered. Only an external interrupt or reset will bring the MPU out of the stop mode. Figure 11 shows a flowchart of the stop function. STOP TCR BIT 7 <= 0 TCR BIT 6 <= 1 CLEAR I BIT N RESET? Y N EXTERNAL INTERRUPT? Y FETCH EXTERNAL INTERRUPT OR RESET VECTOR Figure 11. STOP Function Flowchart Copyright (c) 2002 ENG21108140100 innovASIC The End of ObsolescenceTM www.innovasic.com Customer Support: 1-888-824-4184 Page 13 of 31 IA6805E2 Microprocessor Unit Wait Mode: Data Sheet As of Production Version 00 The wait instruction places the MPU in low power consumption mode. The wait instruction disables clocking of most internal registers. The DS and AS output lines go "low" and the RW_n line goes "high". The multiplexed address/data bus goes to the data input state. The high order address lines remain at the address of the next instruction. External interrupts are enabled by clearing the I bit in the condition code register. All other registers, memory, and I/O remain unaltered. Only an external interrupt, timer interrupt, or reset will bring the MPU out of the wait mode. The timer may be enabled to allow a periodic exit from the wait mode. If an external and a timer interrupt occur at the same time, the external interrupt is serviced first. Then, if the timer interrupt request is not cleared in the external interrupt routine, the normal timer interrupt (not the timer wait interrupt) is serviced since the MPU is no longer in the wait mode. Figure 12 shows a flowchart of the wait function. WAIT OSCILLATOR ACTIVE, CLEAR I BIT, TIMER CLOCK ACTIVE, RESET? N Y EXTERNAL INTERRUPT? Y N TIMER INTERRUPT? (TCR BIT7 = 1) Y N TCR BIT 6 = 0? Y FETCH EXTERNAL INTERRUPT, RESET, OR TIMER INTERRUPT (FROM WAIT MODE ONLY) N Figure 12. WAIT Function Flowchart Copyright (c) 2002 ENG21108140100 innovASIC The End of ObsolescenceTM www.innovasic.com Customer Support: 1-888-824-4184 Page 14 of 31 IA6805E2 Microprocessor Unit Timer: Data Sheet As of Production Version 00 The MPU contains a single 8-bit software programmable counter driven by a 7-bit software programmable prescaler. The counter may be loaded under program control and decrements to zero. When the counter decrements to zero, the timer interrupt request bit in the timer control register (TCR7) is set. Figure 13 shows a block diagram of the timer. If the timer mask bit (TCR6) and the interrupt mask bit (I) of the condition code register are cleared, an interrupt request is generated. After completion of the current instruction, the current state of the machine is pushed onto the stack. The timer interrupt vector address is then fetched from locations $1FF8 and $1FF9 and the interrupt routine is executed, unless the MPU was in the WAIT mode in which case the interrupt vector address in locations $1FF6 and $1FF7 is fetched. Power-On-Reset causes the counter to set to $FF. NOTE: 1. Prescaler and counter are clocked on the falling edge of the internal clock (AS) or external input. 2. Counter is written to during Data Strobe (DS) and counts down continuously. TIMER (PIN 37) TIMER_n EXT CLK PRESCALER (7 BITS) COUNTER (8 BITS) INTERRUPT CONTROL 2 - TO - 1 MUX INTERRUPT READ INT CLK ENABLE / DISABLE_n INTERNAL_n / EXTERNAL INTERNAL CLOCK WRITE TCR4 TCR5 TCR3 TCR2 TCR1 TCR0 SETTING TCR3 CLEARS PRESCALER TO / 1 SOFTWARE FUNCTIONS Figure 13. Timer Block Diagram Copyright (c) 2002 ENG21108140100 innovASIC The End of ObsolescenceTM www.innovasic.com Customer Support: 1-888-824-4184 Page 15 of 31 IA6805E2 Microprocessor Unit Data Sheet As of Production Version 00 The counter continues to count past zero, falling from $00 to $FF, and continues. The processor may read the counter at any time without disturbing the count by reading the timer data register (TDR). This allows a program to determine the length of time since a timer interrupt has occurred. The timer interrupt request bit remains set until cleared by software. The interrupt is lost if this happens before the timer interrupt is serviced. The prescaler is a 7-bit divider used to extend the maximum length of the timer. TCR bits 0-2 are programmed to choose the appropriate prescaler output, which is used as the count input. The prescaler is cleared by writing a "1" into TCR bit 3, which avoids truncation errors. The processor cannot write to or read from the prescaler. Timer Input Mode 1: When TCR4 = 0 and TCR5 = 0, the input to the timer is from an internal clock and the timer input is disabled. The internal clock mode can be used for periodic interrupt generation as well as a reference for frequency and event measurement. The internal clock is the instruction cycle clock and is coincident with Address Strobe (AS) except during the wait instruction where it goes low. During the wait instruction the internal clock to the timer continues to run at its normal rate. Timer Input Mode 2: When TCR4 = 1 and TCR5 = 0, the internal clock and timer input signal are ANDed to form the timer input. This mode can be used to measure external pulse widths. The external pulse turns on the internal clock for the duration of the pulse. The count accuracy in this mode is 1 clock. Accuracy improves with longer input pulse widths. Timer Input Mode 3: When TCR4 = 0 and TCR5 = 1, all inputs to the timer are disabled. Timer Input Mode 4: When TCR4 = 1 and TCR5 = 1, the internal clock input to the timer is disabled and the timer input then comes from the external TIMER pin. The external clock can be used to count external events as well as to provide an external frequency for generating periodic interrupts. Copyright (c) 2002 ENG21108140100 innovASIC The End of ObsolescenceTM www.innovasic.com Customer Support: 1-888-824-4184 Page 16 of 31 IA6805E2 Microprocessor Unit TCR (Timer Control Register ($0009)): Data Sheet As of Production Version 00 An 8-bit register that controls functions such as configuring operation mode, setting ratio of the prescaler, and generating timer interrupt request signals. All bits except bit 3 are read/write. Bits TCR5 - TCR0 are unaffected by reset_n. 7 6 5 4 3 2 1 0 TCR7 TCR6 TCR5 TCR4 TCR3 TCR2 TCR1 TCR0 Reset: 0 1 0 0 0 0 0 0 TCR7 - Timer Interrupt Request Used to indicate the timer interrupt when it is logic one. 1 - Set when the counter decrements to zero or under program control. 0 - Cleared on external reset, POR, STOP instruction, or program control. TCR6 - Timer Interrupt Mask Used to inhibit the timer interrupt. 1 - Interrupt inhibited. Set on external reset, POR, STOP instruction, or program control. 0 - Interrupt enabled. TCR5 - External or Internal Selects input clock source. Unaffected by reset. 1 - External clock selected. 0 - Internal clock selected (AS) (fOSC /5). TCR4 - Timer External Enable Used to enable external timer pin or to enable the internal clock. Unaffected by reset. 1 - Enables external timer pin. 0 - Disables external timer pin. Copyright (c) 2002 ENG21108140100 innovASIC The End of ObsolescenceTM www.innovasic.com Customer Support: 1-888-824-4184 Page 17 of 31 IA6805E2 Microprocessor Unit Data Sheet As of Production Version 00 TCR3 - Prescaler Clear Write only bit. Writing a "1" to this bit resets the prescaler to zero. A read of this location always indicates a zero. Unaffected by reset. TCR2, TCR1, TCR0 - Prescaler select bits Decoded to select one of eight outputs of the prescaler. Unaffected by reset. Prescaler TRC2 0 0 0 0 1 1 1 1 TRC1 0 0 1 1 0 0 1 1 TRC0 0 1 0 1 0 1 0 1 RESET /1 /2 /4 /8 /16 /32 /64 /128 Copyright (c) 2002 ENG21108140100 innovASIC The End of ObsolescenceTM www.innovasic.com Customer Support: 1-888-824-4184 Page 18 of 31 IA6805E2 Microprocessor Unit Instruction Set Description Data Sheet As of Production Version 00 The MPU has 61 basic instructions divided into 5 types. The 5 types are Register/memory, readmodify-write, branch, bit manipulation, and control. Register/Memory Instructions: Most of the following instructions use two operands. One is either the accumulator or the index register and the other is obtained from memory. The jump unconditional (JMP) and jump to subroutine (JSR) instructions have no register operand. Function Load A from memory Load X from memory Store A in memory Store X in memory Add memory to A Add memory and carry to A Subtract memory Subtract memory from A with Borrow AND memory to A OR memory with A Exclusive OR memory with A Arithmetic compare A with memory Arithmetic compare X with memory Bit test memory with A (logical compare) Jump Unconditional Jump to subroutine Mnemonic LDA LDX STA STX ADD ADC SUB SBC AND ORA EOR CMP CPX BIT JMP JSR Read-Modify-Write Instructions: These instructions read a memory or register location, modify or test its contents and then write the modified value back to memory or the register. Function Increment Decrement Clear Complement Negate (2's complement) Rotate Left Thru Carry Rotate Right Thru Carry Logical shift left Logical shift right Arithmetic shift right Test for negative or zero Copyright (c) 2002 ENG21108140100 Mnemonic INC DEC CLR COM NEG ROL ROR LSL LSR ASR TST www.innovasic.com Customer Support: 1-888-824-4184 innovASIC The End of ObsolescenceTM Page 19 of 31 IA6805E2 Microprocessor Unit Bit Manipulation Instructions: Data Sheet As of Production Version 00 The MPU is capable of altering any bits residing in the first 256 bytes of memory. An additional feature allows the software to test and branch on the state of any bit within these locations. For test and branch instructions the value of the bit tested is placed in the carry bit of the condition code register. Mnemonic n = 0...7 BRSET n BRCLR n BSET n BCLR n Function Branch if bit n set Branch if bit n clear Set bit n Clear bit n Branch Instructions: If a specific condition is met, the instruction branches. If not, no operation is performed. Function Branch always Branch never Branch if higher Branch if lower or same Branch if carry clear Branch if higher or same Branch if carry set Branch if lower Branch if not equal Branch if equal Branch if half carry clear Branch if half carry set Branch if plus Branch if minus Branch if interrupt mask bit clear Branch if interrupt mask bit set Branch if interrupt line low Branch if interrupt line high Branch to subroutine Mnemonic BRA BRN BHI BLS BCC BHS BCS BLO BNE BEQ BHCC BHCS BPL BMI BMC BMS BIL BIH BSR Copyright (c) 2002 ENG21108140100 innovASIC The End of ObsolescenceTM www.innovasic.com Customer Support: 1-888-824-4184 Page 20 of 31 IA6805E2 Microprocessor Unit Control Instructions: Data Sheet As of Production Version 00 Used to control processor operation during program execution. They are register reference instructions. Function Transfer A to X Transfer X to A Set carry bit Clear carry bit Set interrupt mask bit Clear interrupt mask bit Software interrupt Return from subroutine Return from interrupt Reset stack pointer No-Operation Stop Wait Mnemonic TAX TXA SEC CLC SEI CLI SWI RTS RTI RSP NOP STOP WAIT Copyright (c) 2002 ENG21108140100 innovASIC The End of ObsolescenceTM www.innovasic.com Customer Support: 1-888-824-4184 Page 21 of 31 IA6805E2 Microprocessor Unit Opcode Map Summary: Data Sheet As of Production Version 00 The following table is an opcode map for the instructions used on the MPU. The legend following the table shows how to use the table. Bit Manipulation Branch BTB Hi Low 0 0000 3 1 0001 3 2 0010 3 3 0011 3 4 0100 3 5 0101 3 6 0110 3 7 0111 8 1000 9 1001 A 1010 3 B 1011 C 1100 D 1101 E 1110 3 F 1111 3 0 0000 5 BRSET0 BTB 2 5 BRCLR0 BTB 2 5 BRSET1 BTB 2 5 BRCLR1 BTB 2 5 BRSET2 BTB 2 5 BRCLR2 BTB 2 5 BRSET3 BTB 2 5 BRCLR3 3 BTB 2 5 BRSET4 3 BTB 2 5 BRCLR4 3 BTB 2 5 BRSET5 BTB 2 5 BRCLR5 BTB 2 BSET5 BSC 2 5 BCLR5 BSC 2 BCLR4 BSC 2 5 BPL REL 2 3 BMI REL BCLR3 BSC 2 5 BSET3 BSC 2 5 BEQ REL 2 3 BCLR2 BSC 2 5 BNE REL 2 3 ASR DIR 1 5 BSET2 BSC 2 5 BCS REL 3 ROR DIR 1 5 ASRA INH 1 3 5 RORA INH 1 3 ASRX INH 2 3 3 RORX INH 2 3 ASR IX1 1 6 3 ROR IX1 1 6 ASR IX 5 1 6 ROR IX 5 TAX INH 2 2 STA DIR 3 2 5 LDA IMM 2 2 BCLR1 BSC 2 5 BCC REL 2 3 BIT IMM 2 2 LDA DIR 3 4 STA EXT 3 BSET1 BSC 2 5 BLS REL 2 3 LSR DIR 1 BCLR0 BSC 2 5 BHI REL 3 COM DIR 1 5 LSRA INH 1 5 COMA INH 1 3 LSRX INH 2 3 COMX INH 2 3 LSR IX1 1 3 COM IX1 1 6 LSR IX 2 6 COM IX 1 5 AND IMM 2 2 BIT DIR 3 3 LDA EXT 3 5 STA IX2 2 5 SWI INH 2 10 CPX IMM 2 2 AND DIR 3 3 BIT EXT 3 4 LDA IX2 2 6 STA IX1 1 2 BSET0 BSC 2 5 BRN REL 3 SBC IMM 2 2 CPX DIR 3 3 AND EXT 3 4 BIT IX2 2 5 LDA IX1 1 5 STA IX 1 BSC 1 0001 5 BRA REL 2 3 RTS INH 2 REL 2 0010 3 NEG DIR 1 DIR 3 0011 5 NEGA INH 1 Read-Modify-Write INH 4 0100 3 NEGX INH 2 INH 5 0101 3 NEG IX1 1 IX1 6 0110 6 NEG IX 1 IX 7 0111 5 Control INH 8 1000 9 RTI INH 6 CMP IMM 2 2 SBC 2 SUB IMM 2 2 CMP INH 9 1001 IMM A 1010 2 SUB DIR B 1011 Register/Memory EXT C 1100 3 SUB EXT 3 4 CMP EXT 3 4 SBC EXT 3 4 CPX EXT 3 4 AND IX2 2 5 BIT IX1 1 4 LDA IX 4 7 0111 CPX IX2 2 5 AND IX1 1 4 BIT IX 3 6 0110 3 SBC IX2 2 5 CPX IX1 1 4 AND IX 3 5 0101 3 DIR 3 CMP IX2 2 5 SBC IX1 1 4 CPX IX 3 4 0100 3 DIR 3 DIR 3 4 SUB IX2 2 5 CMP IX1 1 4 SBC IX 3 3 0011 IX2 D 1101 5 SUB IX1 1 4 CMP IX 3 2 0010 IX1 E 1110 4 SUB IX 3 1 0001 IX F 1111 3 0 0000 Hi Low BSET4 BHCC LSL LSLA LSLX LSL LSL BSC 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 5 BHCS REL 2 3 DEC DIR 1 3 ROL DIR 1 5 DECA INH 1 5 ROLA INH 1 3 DECX INH 2 3 ROLX INH 2 3 DEC IX1 1 3 ROL IX1 1 6 DEC IX 6 ROL IX 5 5 2 2 3 4 5 4 3 8 1000 CLC EOR EOR EOR EOR EOR EOR 1 INH 2 IMM 2 DIR 3 EXT 3 IX2 2 IX1 1 IX 2 SEC 1 INH 2 2 CLI 1 INH 2 2 ORA IMM 2 2 ADC IMM 2 2 ORA DIR 3 3 2 ADC DIR 3 3 ORA EXT 3 4 3 ADC EXT 3 4 ORA IX2 2 5 4 ADC IX2 2 5 ORA IX1 1 4 5 ADC IX1 1 4 ORA IX 3 4 ADC IX 3 A 1010 3 9 1001 3 1 B 1011 SEI ADD ADD ADD ADD ADD ADD INH 2 IMM 2 DIR 3 EXT 3 IX2 2 IX1 1 IX 2 3 4 3 2 C 1100 JMP JMP JMP JMP JMP 2 DIR 3 EXT 3 IX2 2 IX1 1 IX 5 JSR DIR 3 3 LDX DIR 3 4 STX 2 DIR 3 STX EXT 3 LDX EXT 3 5 STX IX2 2 6 JSR EXT 3 4 LDX IX2 2 6 STX IX1 1 7 6 5 D 1101 JSR JSR JSR IX2 2 IX1 1 IX 5 LDX IX1 1 5 STX IX 4 LDX IX 4 F 1111 3 E 1110 5 BRSET6 3 BTB 2 5 BRCLR6 3 BTB 2 5 BRSET7 BTB 2 5 BRCLR7 BTB 2 5 3 5 3 3 6 5 BSET6 BMC INC INCA INCX INC INC BSC 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 5 BCLR6 BSC 2 5 BSET7 BSC 2 5 BCLR7 BSC 2 BIH REL 2 BIL REL 3 CLR DIR 1 5 CLRA INH 1 3 CLRX 3 CLR IX1 1 INH 2 6 CLR IX 1 5 WAIT 1 3 4 3 3 6 4 BMS TST TSTA TSTX TST TST REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 3 STOP INH 2 2 2 RSP 1 INH 2 6 NOP BSR 1 INH 2 IMM 2 2 LDX 2 2 TXA INH IMM 2 Abbreviations for Address Modes: INH A X IMM DIR EXT Inherent Accumulator Index Register Immediate Direct Extended REL BSC BTB IX IX1 IX2 Legend: Relative Bit set/clear Bit test and branch Indexed, no offset Indexed, 1 byte offset Indexed, 2 byte offset INH 1 F 1111 Mnemonic Bytes # of Cycles Opcode in Hexadecimal Opcode in Binary 3 SUB IX 1 0 0000 Address Mode Copyright (c) 2002 ENG21108140100 innovASIC The End of ObsolescenceTM www.innovasic.com Customer Support: 1-888-824-4184 Page 22 of 31 IA6805E2 Microprocessor Unit AC/DC Parameters Absolute maximum ratings: Supply Voltage (VDD)............................................................-0.3V to 6V Input Pin Voltage (VIN)..........................................-0.3 to VDD+0.3V Operating Temperature...............................................-40C to 85C Storage temperature Range (Tstg).........................................- 55C to 150C ESD Protection (HBM)......................................................5000V Data Sheet As of Production Version 00 Note: The specifications indicate levels where permanent damage to the device may occur. Functional operation is not guaranteed under these conditions. Operation at absolute maximum conditions for extended periods may adversely affect the long-term reliability of the device. DC Characteristics (VDD=4.5 to 5.5 Vdc, VSS=0, TA=TL to TH), unless otherwise specified DC CHARACTERISTICS Symbol V DD V OL V OH IO L I OH V IH V IL I IH II L VtVt+ Parameter Supply Voltage Output Voltage, I LOAD 2m A Min 4.5 3.5 2 1.1 Max 5.5 0.4 2 -2 0.8 1 -1 1.87 Unit V V V mA mA V V A A V V Output Current High Level input Voltage Low Level input Voltage High Level input Current Low Level input Current Schmitt Negative Threshold Schmitt Positive Threshold Frequency of Operation f OSC f OSC Crystal External Clock DC 5 5 MHz MHz Copyright (c) 2002 ENG21108140100 innovASIC The End of ObsolescenceTM Page 23 of 31 www.innovasic.com Customer Support: 1-888-824-4184 IA6805E2 Microprocessor Unit Control Timing VSS=0V, TA=TL to TH Data Sheet As of Production Version 00 Parameters I/O Port Timing - Input Setup Time (Figure 14) Input Hold Time (Figure 14) Output Delay Time (Figure 14) Interrupt Setup Time (Figure 15) Crystal Oscillator Startup Time (Figure 16) Wait Recovery Startup Time (Figure 17) Stop Recovery Startup Time (Figure 18) Required Interrupt Release (Figure 15) Timer Pulse Width (Figure 17) Reset Pulse Width (Figure 16) Timer Period (Figure 17) Interrupt Pulse Width Low (Figure10) Interrupt Pulse Period (Figure 10) Oscillator Cycle Period (1/5 of tCYC) (Figure 3) OSC1 Pulse Width High (Figure 3) OSC1 Pulse Width Low (Figure 3) Sym tPVASL tASLPX tASLPV TILASL tOXOV tIVASH tILASH tDSLIH tTH, tTL tRL tTLTL tILIH tILIL tOLOL tOH tOL VDD = 5.0V 10% f OSC = 5MHz Min Typ Max 196 0 0.4 0.5 1.05 1.0 1.0 * 200 75 75 5 0 100 2 2 1.0 - Unit ns ns ns s ms s s s tCYC s tCYC tCYC tCYC ns ns ns *The minimum period of tILIL should not be less than the number of tCYC cycles it takes to execute the interrupt service routine plus 20 tCYC cycles. Copyright (c) 2002 ENG21108140100 innovASIC The End of ObsolescenceTM Page 24 of 31 www.innovasic.com Customer Support: 1-888-824-4184 IA6805E2 Microprocessor Unit Bus Timing VSS=0V, TA=TL to TH (Figure 19) Data Sheet As of Production Version 00 Num 1 2 3 4 8 9 11 16 17 18 19 21 23 24 25 26 27 28 Parameters Cycle Time Pulse Width, DS Low Pulse Width, DS High Clock Transition RW_n Non-Muxed Address Hold RW_n Delay From DS Fall Non-Muxed Address Delay From AS Rise MPU Read Data Setup Read Data Hold MPU Data Delay, Write Write Data Hold Muxed Address Delay From AS Rise Muxed Address Valid to AS Fall Muxed Address Hold Delay DS Fall to AS Rise Pulse Width, AS High Delay, AS Fall to DS Rise VDD = 5.0V 10% f OSC = 5MHz 1 TTL, 100pF Load Min Max 1000 DC 587 403 4 9 97 40 11 18 0 0 204 26 185 103 190 203 185 - Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns VLOW = 0.8V, VHIGH = VDD - 2.0V, VDD = 5.0V 10% TA = TL to TH, C L on Port = 50pF, fOSC = 5MHz ADDRESS_STROBE tPVASL PORT_INPUT tASLPV PORT_OUTPUT *NOTE tASLPX *Note: The address strobe of the first cycle of the next instruction. Figure 14. I/O Port Timing Copyright (c) 2002 ENG21108140100 www.innovasic.com Customer Support: 1-888-824-4184 innovASIC The End of ObsolescenceTM Page 25 of 31 IA6805E2 Microprocessor Unit Data Sheet As of Production Version 00 AS n0 DS n1 n2 n3 n4 n5 n6 n7 n8 n9 (NOTE) TDSLIH ADD_BUS_UNMUX[8:12] NEXT OP CODE ADDRESS INT ROUTINE LAST ADDRESS INT ROUTINE STARTING ADDRESS 1F (FF) 1F (FF) T ILASL IRQ_N__TCR7_N MUX_ADD_DATA[0:7] NEXT OP CODE SP PCL SP-1 PCH SP-2 X SP-3 A SP-4 CC NEW PCH NEW PCL 80 FA (IRQ) FB (IRQ) 1ST OP F8 (TIMER) F9 (TIMER) INT ROUTINE RTI OP CODE RW_N Note: tDSLIH- the interrupting device must release the IRQ_N line within this time to prevent subsequent recognition of the same interrupt. Figure 15. IRQ_n and TCR 7_N Interrupt Timing Figure 16. Power-On-Reset and RESET_n Timing Copyright (c) 2002 ENG21108140100 innovASIC The End of ObsolescenceTM Page 26 of 31 www.innovasic.com Customer Support: 1-888-824-4184 IA6805E2 Microprocessor Unit t TL t TH INT_EXT_CLK TIMER COUNTER=$00 Data Sheet As of Production Version 00 t TLTL TCR7 tIVASH AS n0 DS A[12:8] OP CODE ADDRESS OP CODE ADDR n1 n2 n3 n4 n5 n6 n7 ADDRESS + 1 1F (FF) 1F (FF) INT ROUTINE STARTING ADDRESS ADDR + 1 B[7:0] 8F WAIT OP CODE SP PCL SP-1 PCH SP-2 X SP-3 A SP-4 CC F6 NEW PCH F7 NEW PCL 1ST OP CODE INT ROUTINE RW_N Figure 17. Timer Interrupt After WAIT Instruction Timing TIMER COUNTER=$00 t TL t TH INT_EXT_CLK t TLTL TCRB7 tIVASH AS n0 DS A[12:8] OP CODE ADDRESS OP CODE ADDR n1 n2 n3 n4 n5 n6 n7 ADDRESS + 1 1F (FF) 1F (FF) INT ROUTINE STARTING ADDRESS ADDR + 1 B[7:0] 8E STOP OP CODE SP PCL SP-1 PCH SP-2 X SP-3 A SP-4 CC F6 NEW PCH F7 NEW PCL 1ST OP CODE INT ROUTINE RW_N Figure 18. Interrupt Recovery From STOP Instruction Timing Copyright (c) 2002 ENG21108140100 www.innovasic.com Customer Support: 1-888-824-4184 innovASIC The End of ObsolescenceTM Page 27 of 31 IA6805E2 Microprocessor Unit Data Sheet As of Production Version 00 4 27 AS DS 4 8 RW_n 11 9 A[12:8] 23 16 26 4 4 1 2 28 3 4 26 4 8 11 9 21 B[7:0] WRITE 18 B[7:0] READ 25 VALID ADDR 24 25 19 VALID WRITE DATA 17 VALID READ DATA 21 23 VALID ADDR 18 23 Figure 19. Bus Timing Copyright (c) 2002 ENG21108140100 innovASIC The End of ObsolescenceTM Page 28 of 31 www.innovasic.com Customer Support: 1-888-824-4184 IA6805E2 Microprocessor Unit Packaging Information PDIP Packaging TOP Data Sheet As of Production Version 00 E1 E LEAD 1 IDENTIFIER eA 1 LEAD COUNT DIRECTION C eB SIDE VIEW (WIDTH) Lead Count 40 (in Inches) D A Symbol A A1 B A1 MIN .015 .015 .040 .008 1.980 .580 .520 .100 TYP .580 .100 MIN MAX .200 .020 .060 .012 2.065 .610 .560 B1 C L B B1 e D E E1 e eA eB L SIDE VIEW (LENGTH) .686 Copyright (c) 2002 ENG21108140100 innovASIC The End of ObsolescenceTM Page 29 of 31 www.innovasic.com Customer Support: 1-888-824-4184 IA6805E2 Microprocessor Unit PLCC Packaging Data Sheet As of Production Version 00 D 1.22/1.07 2 PLCS PIN 1 IDENTIFIER & ZONE D1 E3 D3 TOP VIEW BOTTOM VIEW .81 / .66 E1 E LEAD COUNT 44 (in Millimeters) Symbol SEATING PLANE A MIN 4.20 2.29 16.51 14.99 MAX 4.57 3.04 16.66 16.00 A A1 A1 D1 e .51 MIN. .53 / .33 R 1.14 / .64 .10 D2 D3 E1 E2 12.70 BSC 16.51 14.99 16.66 16.00 D2 / E2 SIDE VIEW E3 e D E 12.70 BSC 1.27 BSC 17.40 17.40 17.67 17.65 Copyright (c) 2002 ENG21108140100 innovASIC The End of ObsolescenceTM Page 30 of 31 www.innovasic.com Customer Support: 1-888-824-4184 IA6805E2 Microprocessor Unit Ordering Information Data Sheet As of Production Version 00 The IA6805E2 is available in two package styles listed in the table below. Other packages and temperature grades may be available for additional cost and lead time. Package Type 40 Lead Plastic DIP, 600 mil wide 44 Lead Plastic Leaded Chip Carrier Temperature Grade Industrial Industrial Order Number IA6805E2-PDW40I IA6805E2-PLC44I Cross Reference to Original Manufacturers innovASIC Part Number IA6805E2-PDW40I Motorola(R) Part Number q q Harris(R) Part Number q q MC146805E2CP MC146805E2P MC146805E2CFN MC146805E2FN CDP6805E2CE CDP6805E2E CDP6805E2CQ CDP6805E2Q IA6805E2-PLC44I q q q q Errata Production Version 00 1. Functional differences between IA6805E2 and Harris and Motorola Versions: Stop mode on IA6805E2 will not halt oscillator. Recovery from stop will be quicker. 2. Observations: A. Original data sheets for Motorola and Harris are inconsistent when describing timer input mode 2. Original parts and InnovASIC will AND together the timer input with the inverse of the internal clock (AS). B. Original Harris part would unpredictably "pre-increment" timer counter when writing to timer registers. IA6805E2 will not. C. Original Harris part displays incorrect address on external pins during intermediate cycles (not a functional problem) of multi-cycle instructions when accessing memory at page boundaries. IA6805E2 will not. D. Execution of illegal op-codes on the IA6805E2 will force a system reset. On the original Harris and Motorola parts, execution of illegal op-codes would produce unpredictable results. Copyright (c) 2002 ENG21108140100 innovASIC The End of ObsolescenceTM Page 31 of 31 www.innovasic.com Customer Support: 1-888-824-4184 |
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